Sunday November 23rd 2014

Archived news

IEEE UK and Ireland Circuits and Systems Chapter

Activities

We are happy to announce that we are organising and sponsoring:

IEEE UK and Ireland Section Circuits and System Chapter on 10th October 2014. The Lecture
is from Dr. Ravinder S. Dahia, University of Glasgow

The Lecture will be given at the University of Westminster, 115 New Cavendish Street, London W1W 6UW in Room: C1.04  from 16:00-17:00 hrs where all IEEE members and non-members will be welcome to attend:
Lecture Details:

An IEEE UK and Ireland Section Sponsored talk

“Conformable Electronics”
The microelectronics technology and subsequent miniaturization have led to a revolution in computer and communication that began almost immediately after the transistor was invented. The exponential rate of miniaturization led technological advancement that is described in Moore’s Law has been propelled by $1Tr of investment over 50 years. Recent advances in the field, propelled by applications such as wearable electronics and emerging areas such as internet of things, relate to realizing sensitive electronic systems on unconventional substrates such as plastics or paper that can be wrapped around curved surfaces of food packages and the body of a robot or artificial limbs. Early attempts to achieve conformable electronic systems primarily followed the flexible printed circuit boards (PCB) route, offering a limited degree of mechanical flexibility. Recent efforts to address these challenges include fabricating sensing and electronic components directly on the flexible substrates or on thin silicon wafers. A variety of solutions, ranging from TFTs to printed electronics have appeared using a wide variety of materials, including organic and inorganic semiconductors. This lecture will present these developments with a focus on the high-performance bendable and conformable electronics. The advent of fully flexible electronic systems will be a great leap in technology, as it will open the door to the next-generation electronic environment based on bendable and wearable devices. Exciting new opportunities lie in pursuing the non-roadmap “More than Moore” technology to discover and exploit the as yet unfulfilled potential of electronics in markets and applications that have historically lain outside the realm of microelectronics. This lecture will cover our research on flexible electronics, supported by European Commission and EPSRC funded projects such as CONTEST, PRINTSKIN and FLEXELDEMO.

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Brief biography for Dr. Ravinder Dahia
Ravinder Dahiya is a Senior Lecturer and EPSRC Research Fellow at School of Engineering, University of Glasgow, U.K. He received Ph.D. from Italian Institute of Technology, Genoa (Italy). In past, he worked at University of Delhi (India), Italian Institute of Technology, Genoa (Italy), Fondazione Bruno Kessler, Trento (Italy), and Univ. of Cambridge (UK).

His multidisciplinary research interests include Flexible and Printable Electronics, Electronic Skin, Tactile Sensing, and wearable electronics. He has published more than 90 research articles, one book (Robotic Tactile Sensing – Technologies and System) and holds 2 patents. He has worked on the many international projects (ROBOSKIN, RobotCub, Flexsensotronics). Currently he is leading a European Commission funded Initial Training Network (CONTEST) and EPSRC Fellowship for Growth – Printable Tactile Skin (PRINTSKIN) and EPSRC First Grant project (FLEXELDEMO).

He is Senior Member of IEEE and member of IEEE Sensors Council AdCom. He is on Editorial Boards of IEEE Transactions on Robotics and IEEE Sensors Journal. He has guest edited 4 Special Journal Issues.

Ravinder has received EPSRC fellowship and Marie Curie Fellowship. He was awarded with the University Gold Medal for securing First Class First Position in the University and received best paper awards two times in the IEEE sponsored conferences.
Personal website – www.rsdahiya.com
Official webpage – http://www.gla.ac.uk/schools/engineering/staff/ravinderdahiya/

We are happy to announce that we are organising and sponsoring:

IEEE UK and Ireland Section Circuits and System Chapter on 23rd September 2014. The Lecture
is from Professor Andrew G. Dempster, University of New South Wales Australia

The Lecture will be given at the University of Westminster, 115 New Cavendish Street, London W1W 6UW in the Small Lecture Theatre from 13:00-14:00 hrs where all IEEE members and non-members will be wellcome to attend:
Lecture Details:

An IEEE UK and Ireland Section Sponsored talk

Off-Earth Mining

Mining is central to the so-called “NewSpace” or “Space 2.0″ paradigm, where activity in space is becoming more overtly commercial. Two asteroid mining companies, Deep Space Industries and Planetary Resources, are planning launches of spacecraft in the next two years. The steps to mining in space are similar to terrestrial mining: exploration, extraction, processing, distribution, but the activities in each of those steps are distinctly different. This talk looks at some of the diverse research problems involved in mining in space: at UNSW, researchers from six engineering schools (Electrical, Mining, Mechanical, Civil, Computing, and Photovoltaics) and five faculties (Engineering, Science, Law, Business, Arts) are exploring the unanswered questions in this exciting new area. This talk will explain the background to some of this work and examine some research case studies.

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Brief biography for Prof. Andrew G. Dempster

Professor Andrew Dempster is Director of the Australian Centre for Space Engineering Research (ACSER) in the School of Electrical Engineering and Telecommunications at the University of New South Wales (UNSW). He has a BE and MEngSc from UNSW and a PhD from the University of Cambridge in efficient circuits for signal processing arithmetic. He was system engineer and project manager for the first GPS receiver developed in Australia in the late 80s and has been involved in satellite navigation ever since. His current research interests are in satellite navigation receiver design and signal processing, areas where he has six patents, and new location technologies. He is leading the development of space engineering research at ACSER.

We are happy to announce that we are organising and sponsoring:

IEEE UK and Ireland Section Circuits and System Chapter December 2103 Distinguished Lecturer Series
From Professor Joseph R. Cavallaro of Rice University, USA.

Two Lectures will be given in this Lecture Series, at the following venues and dates where all IEEE members and non-members will be wellcome:
Lecture Schedule and venues:

09 December 2013: Lecture#1, Imperial College London, Exhibition Road, London SW7 2AZ,
Dennis Gabor Seminar Room (611), EEE Department,
From: 16:00:00-17:00:00
Contact Person: David Thomas (<d.thomas1@imperial.ac.uk>)

10 December 2013: Lecture#2, Queen Mary, University of London, Godward Square, London E1 4FZ,
Second-floor Seminar Room, ITL (Informatics Teaching Labs)
Directions to QMUL can be found here: http://www.qmul.ac.uk/about/howtofindus/mileend/
ITL building is no:5 (bottom-left) on the map: http://www.qmul.ac.uk/docs/about/26065.pdf
From: 16:00:00-17:00:00
Contact Person: Miles Hansard (<miles.hansard@qmul.ac.uk>)

11December 2013: Lecture#2, University College Dublin, Complex & Adaptive Systems Laboratory
Room 3 D, 8 Belfield Office Park, Beaver Row, Clonskeagh, Dublin 4
School of Computer Science and Informatics,
From: 15:00:00-16:00:00
Contact Person: Chris Bleakley(<chris.bleakley@ucd.ie>)

12 December 2013: Lecture#1, Queens University Belfast, Ashby Building,
Stranmillis Road Belfast, BT9 5AH,
ECIT Seminar Room,
From: 11:00:00-12:00:00
Contact Person: Roger Woods(<r.woods@qub.ac.uk>)

Lecture#1 : Rapid Prototyping of Embedded VLSI Systems
Lecture#2 : VLSI Architectures for Wireless Communication Systems

Lecture#1 Abstract:
In this talk, we focus on tools and methodologies for design, simulation, and prototyping of VLSI, FPGA and reconfigurable processors. This talk presents a rapid prototyping design methodology for the design and implementation of digital signal processing (DSP) algorithms and systems on embedded hardware platforms, such as cellular telephones and wireless networks. The process begins with a high level algorithmic description in a design and simulation language and then is mapped and synthesized to a number of targets including ASIC, FPGA, and DSP systems. The challenge is to exploit the data parallelism in the algorithms to achieve high performance in low-power systems.
At Rice University, we are building a wireless open access reseach platform systems testbed, called WARP, that supports end-to-end prototyping research. The research goal is to explore the complexity and performance of signal processing architectures for high data rate wireless systems using multiple transmit and receive antennas. The testbed includes high performance DSP processors integrated with high density FPGA devices. These digital devices are in turn connected via high speed A/D and D/A data converters to 2.4 GHz radios. The lab also contains wireless channel emulators that allow the study of typical wireless channels observed in urban and rural environments. In this talk, we will present the tools and design methodologies in the context of embedded systems design. We will describe an example receiver system prototype using tools from the Mathworks, Mentor Graphics, National Instruments, Texas Instruments, and Xilinx. Application of these design methodologies to the design of future DSP systems will shorten development time and improve the efficiency of the systems.

Lecture#2 Abstract:

In this talk, we discuss the challenges of mobile wireless systems in terms of algorithms, area, power, and data rate. The integrated realization of advanced signal processing algorithms and architectures has led to rapid advances in wireless communication systems. The goals of high data rates and low power consumption combined with flexibility and reconfigurability present great challenges for VLSI architectures for baseband processors at the core of all mobile wireless devices.
At the Center for Multimedia Communication at Rice University, we have a comprehensive focus on systems, architectures, and implementations. In this talk, we will describe current research directions in high data rate algorithms for the physical layer of wireless cellular and wireless local area networks. The flexible mapping of these algorithms to low-power VLSI architectures integrates research in communications, signal processing and computer architecture. The key digital baseband algorithms include channel equalization and estimation, detection, and decoding with mappings to configurable low-power baseband VLSI co-processors. We also present current research on a family of multi-cluster programmable VLIW processors for wireless system. The goal is to provide advanced architectures for the next generation of mobile wireless networks.

Brief bio of Professor Cavallaro

Joseph R. Cavallaro (S’78, M’82, SM’05) received the B.S. degree from the University of Pennsylvania, Philadelphia, Pa, in 1981, the M.S. degree from Princeton University, Princeton, NJ, in 1982, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1988, all in electrical engineering. From 1981 to 1983, he was with AT&T Bell Laboratories, Holmdel, NJ. In 1988, he joined the faculty of Rice University, Houston, TX, where he is currently a Professor of electrical and computer engineering. His research interests include computer arithmetic, VLSI design and microlithography, and DSP and VLSI architectures for applications in wireless communications. During the 1996–1997 academic year, he served at the National Science Foundation as Director of the Prototyping Tools and Methodology Program. He was a Nokia Foundation Fellow and a Visiting Professor at the University of Oulu, Finland in 2005 and continues his affiliation there as an Adjunct Professor. He is currently the Director of the Center for Multimedia Communication at Rice University. He is a Senior Member of the IEEE and a Member of the IEEE SPS TC on Design and Implementation of Signal Processing Systems and the IEEE CAS TC on Circuits and Systems for Communications. He is currently an Associate Editor of the IEEE Transactions on Signal Processing, the IEEE Signal Processing Letters, and the Journal of Signal Processing Systems. He was Co-chair of the 2004 Signal Processing for Communications Symposium at the IEEE Global Communications Conference and General/Program Co-chair of the 2003, 2004, and 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), General/Program Co-chair for the 2012, 2014 ACM/IEEE GLSVLSI, and Finance Chair for the 2013 IEEE GlobalSIP conference
We are happy to announce that we are co-sponsoring:

Analog Design Challenges in Nanometer CMOS Technologies

A lecture by
Prof. Willy Sansen
Katholieke Universiteit Leuven, Belgium
Monday, 3 June 2013, 14:00-16:00
Cambridge Silicon Radio Limited, Churchill House, Cambridge Business Park,
Cowley Road, Cambridge, CB4 0WZ

Sponsored by IEEE Solid State Circuits Society and Co-sponsored by
Cambridge Silicon Radio (CSR) and
IEEE Circuits and Systems (UK and Ireland Chapter)

Abstract: Many More-than Moore applications such as sensor interfaces, biomedical and automotive applications, use Nanometer CMOS technologies. They affect speed, noise and mismatch. Moreover the supply voltage is reduced to values below 1 Volt, creating new challenges for both analog and mixed-signal circuit design. In this presentation, an overview is given of these new applications, followed by a discussion of the limitations such as noise and distortion. A number of low-voltage amplifiers/filters configurations are then discussed, including Analog-to-Digital Converters.

Prof. Willy Sansen has a PhD degree from the University of California, Berkeley in 1972. Since 1980 he has been full professor at the Catholic University of Leuven, in Belgium, where he has headed the ESAT-MICAS laboratory on analog design from 1984 to 2008. He has been supervisor of 63 PhD theses and has authored and coauthored more than 635 publications and sixteen books, among which the slide based “Analog Design Essentials” (Springer 2006). He was program chair of the ISSCC-2002 conference and is now Past-President of the IEEE Solid-State Circuits Society. In 2011 he received the D.O Pederson Award from the IEEE Solid-State Circuits Society. He is a Life Fellow of the IEEE.

Admission is free but space at this event is limited. Preregister by emailing Hashem.Zare-Hoseini@csr.com

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We are happy to announce that we are co-sponsoring:

The 5th International Conference on Imaging for Crime Detection and Prevention (ICDP – 13)

http://www.icdp-conf.org/

16th-17th December 2013, London, UK.

This conference follows the successful IDSS (Intelligent Distributed Surveillance Systems) events held in 2003 and 2004 and ICDP 2005, 2006, 2009 and 2011, to bring together researchers, industry, end-users, law-enforcing agencies and citizens groups to share experiences and explore areas where additional research, development and better working practices are needed, identify possible collaboration and consider the societal impact of such technologies.

The 5th International Conference on Imaging for Crime Detection and Prevention (ICDP-13) aims to create an important networking forum in which participants can discuss the present and future of image-based technologies for crime detection and prevention.

ICDP (and its predecessor IDSS) has traditionally been a special meeting point of different disciplines (computer science, social science, engineering, management, etc.) and an opportunity for a wide range of stakeholders to discuss the many different aspects of the application of imaging technologies in this socially crucial domain.

Paper submission timetable

1 September 2013 Submission of full papers (6 pages)
25 October 2013
Notification of acceptance
11 November 2013 Submission of camera-ready papers

________________________________________________________________

PORTABLE POWER MANAGEMENT - An IEEE CAS Distinguished Lecture by Prof. Franco Maloberti, University of Pavia, Italy. [Details]

LOW POWER DATA CONVERTERS - An IEEE CAS Distinguished Lecture by Prof. Franco Maloberti, University of Pavia, Italy. [Details]

Massive Scale Electronics for “Internet of Things” Applications
a lecture by Prof. Federico Alimenti of the University of Perugia
Thursday, 8th of March 2012, 12:30AM-13.30PM
University of Westminster, Copland Building, Room N1.112
Sponsored by IEEE Circuits and Systems and Instrumentation and
Measurement and Co-sponsored by Solid-State Circuits Society UK and Ireland

Abstract – In the era of “Internet of Things” more and more electronics will be spread over the entire
planet. The consequence of this will be an increase of the pollution caused by the huge amount of
conventional electronic devices not correctly recycled. An alternative approach to ease this problem will be to
re-think massive-scale electronics starting directly from the eco-compatibility. This lecture will review the
present state-of-the-art of “green” electronics having in mind, as a typical device, an autonomous
wireless sensor, fabricated with organic semiconductors on a paper substrate. RFID approach and
energy harvesting concepts will be discussed showing that the basic “bricks” are in part available. Finally
the future application scenario will be addressed to several examples like a fully-organic harmonic RFID
tag and a “smart tile” for the localization of persons in buildings.

Federico Alimenti – received the Laurea degree (summa cum laude) and the PhD degree in electronic
engineering from the University of Perugia, Italy, in 1993 and 1997 respectively. In 1993 he held a
scholarship from Daimler Benz Aerospace, Ulm, Germany. In 1996 he was awarded Young Scientist from
URSI (International Union of Radio Science). He was visiting scientist at the Lehrstuhl für
Hochfrequenztechnik of the Technical University of Munich, Munich, Germany. From 2001 he is an Assistant
Professor of Electronics at the University of Perugia. His research interests concern the modelling, design
and experimental characterization of microwave integrated circuits in CMOS and Si/SiGe BiCMOS
technologies. He is a Senior IEEE member. He is serving as reviewer for several IEEE conferences and
journals (Microwave and Wireless Component Letters, Transaction on Microwave Theory and Techniques,
Transaction on Advanced Packaging, Transaction on Circuits and Systems I, …). Dr. Alimenti was in the EU
Network of Excellence TARGET (Top Amplifier Research Group in a European Team). He is a consultant for
industry. He is the scientific coordinator of the University of Perugia Research Unit for the ARTEMOS project,
ENIAC, call3, 2010. He has authored and/or co-authored more than 100 papers in refereed journals and
conference proceedings. He is co-author of one encyclopaedia item and four book chapters. His current Hindex
is 7 (ISI journals).

Contact us /Committee

Chairperson

Izzet Kale
kalei@wmin.ac.uk

Lecture#1 Abstract:
In this talk, we focus on tools and methodologies for design, simulation, and prototyping of VLSI, FPGA and reconfigurable processors. This talk presents a rapid prototyping design methodology for the design and implementation of digital signal processing (DSP) algorithms and systems on embedded hardware platforms, such as cellular telephones and wireless networks. The process begins with a high level algorithmic description in a design and simulation language and then is mapped and synthesized to a number of targets including ASIC, FPGA, and DSP systems. The challenge is to exploit the data parallelism in the algorithms to achieve high performance in low-power systems.
At Rice University, we are building a wireless open access reseach platform systems testbed, called WARP, that supports end-to-end prototyping research. The research goal is to explore the complexity and performance of signal processing architectures for high data rate wireless systems using multiple transmit and receive antennas. The testbed includes high performance DSP processors integrated with high density FPGA devices. These digital devices are in turn connected via high speed A/D and D/A data converters to 2.4 GHz radios. The lab also contains wireless channel emulators that allow the study of typical wireless channels observed in urban and rural environments. In this talk, we will present the tools and design methodologies in the context of embedded systems design. We will describe an example receiver system prototype using tools from the Mathworks, Mentor Graphics, National Instruments, Texas Instruments, and Xilinx. Application of these design methodologies to the design of future DSP systems will shorten development time and improve the efficiency of the systems.

Lecture#2 Abstract:

In this talk, we discuss the challenges of mobile wireless systems in terms of algorithms, area, power, and data rate. The integrated realization of advanced signal processing algorithms and architectures has led to rapid advances in wireless communication systems. The goals of high data rates and low power consumption combined with flexibility and reconfigurability present great challenges for VLSI architectures for baseband processors at the core of all mobile wireless devices.
At the Center for Multimedia Communication at Rice University, we have a comprehensive focus on systems, architectures, and implementations. In this talk, we will describe current research directions in high data rate algorithms for the physical layer of wireless cellular and wireless local area networks. The flexible mapping of these algorithms to low-power VLSI architectures integrates research in communications, signal processing and computer architecture. The key digital baseband algorithms include channel equalization and estimation, detection, and decoding with mappings to configurable low-power baseband VLSI co-processors. We also present current research on a family of multi-cluster programmable VLIW processors for wireless system. The goal is to provide advanced architectures for the next generation of mobile wireless networks.

Brief bio of Professor Cavallaro
Joseph R. Cavallaro (S’78, M’82, SM’05) received the B.S. degree from the University of Pennsylvania, Philadelphia, Pa, in 1981, the M.S. degree from Princeton University, Princeton, NJ, in 1982, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1988, all in electrical engineering. From 1981 to 1983, he was with AT&T Bell Laboratories, Holmdel, NJ. In 1988, he joined the faculty of Rice University, Houston, TX, where he is currently a Professor of electrical and computer engineering. His research interests include computer arithmetic, VLSI design and microlithography, and DSP and VLSI architectures for applications in wireless communications. During the 1996–1997 academic year, he served at the National Science Foundation as Director of the Prototyping Tools and Methodology Program. He was a Nokia Foundation Fellow and a Visiting Professor at the University of Oulu, Finland in 2005 and continues his affiliation there as an Adjunct Professor. He is currently the Director of the Center for Multimedia Communication at Rice University. He is a Senior Member of the IEEE and a Member of the IEEE SPS TC on Design and Implementation of Signal Processing Systems and the IEEE CAS TC on Circuits and Systems for Communications. He is currently an Associate Editor of the IEEE Transactions on Signal Processing, the IEEE Signal Processing Letters, and the Journal of Signal Processing Systems. He was Co-chair of the 2004 Signal Processing for Communications Symposium at the IEEE Global Communications Conference and General/Program Co-chair of the 2003, 2004, and 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), General/Program Co-chair for the 2012, 2014 ACM/IEEE GLSVLSI, and Finance Chair for the 2013 IEEE GlobalSIP conference.